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SelfclockedCorrelator

Self clocked correlator implemented in FPGA. 2010-09-07

Project goals Design and implementation of a self clocked correlator for wireless sensor networks and RFID applications.

Background A low power detector provides conversion from AM-signal to baseband signal. The baseband signal is digitized and fed into a self clocked correlator providing an output signal if a specific binary word is found in the bit stream.

Figur 1 Self clocked correlator. Specification Length of binary word 200 bits Bit rate 200 kbit/s Clock recovery bit pattern length 10 bits

Supervisor: Lars Bengtsson, CSE department. Company advisor: Emil Nilsson, Lepton Radio.

Tentative and rough time plan Week 1-3 Literature study, Development of detailed time plan Week 4-9 VHDL modelling, Simulation, Verification. Week 10-16 FPGA prototyping and verification. Week 17-20 Buffer time, report writing

Contact: Lars Bengtsson, CSE department, labe@chalmers.se

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Page last modified on September 09, 2010, at 11:54 AM