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Characterization of Supply-Sensitivity of Digital Gates

Almost all of today's integrated circuit design efforts utilize synchronous digital systems for which corner-based static timing analysis is an integral part of the implementation tool chain. It is then necessary to choose environmental condition extremes such that timing requirements are met with sufficient margin to guarantee correct operation across the full range of the chip's specification for temperature, voltage and process variations. For voltage, the corner based approach implies e.g. analyzing timing at minimum voltage for setup timing relationships. However, by exploiting detailed knowledge of the voltage fluctuations in the power grid, it is possible to reduce timing margins such that the risk of overdesign is reduced.

In recent work, we have proposed a way to accurately characterize logic gates with respect to supply sensitivity, with no need for re-simulating the entire system at the circuit level. A first manuscript describing the method has been accepted for publication. We have identified several ideas for future work which seem suitable for exploration by a talented thesis worker. As the manuscript has not yet been published, it is not possible to describe the method publicly on the web; a preprint of the manuscript is available on request.

We expect good results to be publishable.

The applicant will need good MATLAB and circuit simulation skills (Cadence Spectre). Familiarity with the MATLAB System Identification Toolbox is a plus.

This thesis project will be carried out at Chalmers and work can commence immediately. Please contact Lars Svensson to learn more.