Crib sheet for mixed-signal simulation in Cadence Virtuoso using the 130nm process

Oscar Albinsson (,
January 25, 2010

This document describes how to set up a simulation environment in Cadence Virtuoso for co-simulation of Verilog-AMS, VHDL, and schematic level blocks. Cadence ic-5.1.41.USR5 along with the ies-8.20.014 package have been run on a Red Hat 5 system. The module cmos9gp-9.2 was used along with the start command stm_130. The additional configurations of the modules to be able to run AMS are described in Appendix A and the configurations for VHDL are described in Appendix B. The script for starting Cadence is:
source /chalmers/sw/sup/cse/userinit/tcsh
module add cmos9gp-9.2

A Verilog-AMS block is created in the Library Manager by File->New->Cell View. In the Create New File window the tool is set to VerilogAMS-Editor. After the OK button is pressed, an editor window appears where the code is entered. When the code is written and saved and the editor windows is closed, a symbol for your component will be created (if you are successful); or the HDL Parser Error/Warning window will appear asking if you want to re-edit your code (if something has gone wrong...).

In order to simulate the block, a testbench with a Composer-Schematic view has to be created where the symbol of the Verilog-AMS is instantiated along with the surrounding components that tests its functionality. When the entry of the schematic is done, a config file has to be created with the Hierarchy-Editor. In the New Configuration window, make sure that schematic is entered in View under Top Cell. Click on Use Template... and choose Name AMS_Spectre in the menu, then press OK. Make sure that the view for your Verilog-AMS component is verilogams, save the configuration and close the window.

Open the schematic from the config file and start the Virtuoso Analog Design Environment. Select Setup->Simulator/Directory/Host... in the menu and change Simulator to ams and press OK. Setup your analysis and run it as usual.

Schematic simulation

The transistors are located in the Library devices_symbols where a number of components could be chosen from. Documentation for each of these can be found at; /cab/ce/sw/foundry/stm/hcmos9gp/8.2.1/DK_hcmos9gp_A_M6_3V3_HSLL_8.2.1/doc/UserManual/hcmos9_dkit.pdf

Schematic simulation is done as usual except that the models for the transistors have to be added. This is done in the Virtuoso Analog Design Environment where ''Setup->Model Libraries... is selected. In the Model Library File'' slot, refer to the file: /cab/ce/sw/foundry/stm/hcmos9gp/8.2.1/DK_hcmos9gp_A_M6_3V3_HSLL_8.2.1/MODULES/DKhcmos9gp_A_M6_3V3_HSLL_spectre/CORNERS/mosfet.scs

In the Section (opt.) box to the right, one of the following corners is entered: TT, FF, SS, SF or FS (I have used FS). Press OK and start your simulation. It is possible to do simulations at the transistor level with ams as well as spectre.


There are a number of ways to create a VHDL block in Cadence Virtuoso, this chapter only describes one of these. First of all, a hdl.var file has to be copied into your work directory. The hdl.var that has been used is located in: /chalmers/sw/sup/cds/ies-8.20.014/IUS82/tools/inca/files/hdl.var

The VHDL code is written in any program capable of producing a .vhd-file and then imported into Cadence Virtuoso. This is done in the icfb by selecting File->Import->VHDL... In the File Name box in the VHDL Import window find the .vhd-file that you created and click on Add >> and select your Target Library Name. When you press OK, a text line appears in the icfb that says “Starting vhdl in background run...”. It will never finish so go to the Library Manager and look in your selected Target Library Name for a Cell that has the same name as your entity in the imported .vhd-file. There should be three different views, namely; behavioral, entity and symbol. Note that the name of the behavioral is dependent on the specified name in your VHDL code.

In order to simulate this block, use the same procedure as described in the Verilog-AMS chapter except that the selected view in the hierarchy-editor should be set to behavioral for the VHDL block.

A problem that occured during the VHDL simulations was that more than one instance of a full adder couldn’t be simulated. This seems to have something to do with how the configuration is done since the following error message was given: *F,CUNOPN: Cannot open 5x configuration (HearingAid.2BitFullAdd_tb:config.

This error message still appeared even if the adders were instantiated in parallell to avoid undefined input signals. Everything did however work fine with more than one D Register connected in series.

Appendix A: AMS Additions

The cmos9gp-9.2 consists of the following modules, environments and paths:
module-whatis Loads the STM ArtistKit 4.6 and Design Kit 9.2 settings with Cadence ic-
module add ic-5.1.41.USR5
module add calibre-2009.1.46
module add star-rcxt-2008.12-SP3
setenv HCMOS9GP /chalmers/sw/sup/cds/hcmos9gp-9.2
prepend-path PATH /cab/ce/sw/vlsi_misc/scripts]
Additions has been done to the ic-5.1.41.USR5 module in order to run Verilog-AMS. This module has the following setup:
set version "5.1.41"
set cdsdir “/chalmers/sw/sup/cds/ic-5.1.41.USR5”
set amshome “/chalmers/sw/sup/ies-8.20.014/IUS82”
setenv AMSHOME $amshome
setenv CDSDIR $cdsdir
setenv LANG C
setenv LC_ALL C
module add license/cadence
prepend-path PATH $cdsdir/tools/jre/bin
prepend-path PATH $cdsdir/tools/bin
prepend-path PATH $cdsdir/tools/dfII/bin
prepend-path PATH $amshome/tools/dfII/bin/
prepend-path PATH $amshome/tools/bin/
The added environment is the $amshome and its related paths which makes it possible to access NCSim. There has been some warnings when paths that points to /tools/dfII/bin and /tools/bin are defined in two different environments which was solved by some so called ''ugly hacks'', where some paths were linked to the correct folders. Lars Kollberg knows exactly how this was done.

Appendix B: VHDL Additions

In order to get the VHDL compilation to work properly the STD and IEEE libraries has to be added. This was done by modifying the cds.lib that is copied when a Cadence directory is created. The following line were added:
include /chalmers/sw/sup/cds/ies-8.2.014/IUS82/tools/inca/files/cds.lib
It is probable that the paths for the AMS described in Appendix A are mandatory in order to get the VHDL simulations to work.