Documentation for ST Micro 0.12u design flow
Licenses needed for the design flow
* Cadence Virtuoso * Cadence Assura (Optional) * Calibre DRC (Optional)
* ASSURA LVS has shown to have buggs. Several critical design errors have not been found by ASSURA. This might have been improved in newer versions of the Hit-Kit. * ASSURA and DIVA DRC did not report that PADs with the same name/label were shorted. ASSURA DRC has worked as signoff DRC check. * We have still not been able to run logic simulations. Daniel found though a way of creating signal patterns in Spectre.
General Design Tips
* It is not enough to only chose the signals to be plotted to avoid saving all nodes in the circuit. An extra option stating not to save all signals is needed to be applied. (Very useful for large designs). * Make sure to use both DIVA and ASSURA LVS to verify the design. ASSURA has several times shown that it does not detect all mistakes. * Assura requires labels to be put in the PIN Mx layer while DIVA requires pins to be put in the METx pn layer. * Make sure that all the projects work within the same library and that each library has a unique name. Preferably the TOP cell can have the same name as the library. This makes it easier to assemble the final chip since only one library per group has to be added and it is easy to find the TOP cell. * In the final design all pads have to have unique names in order to not get DRC violations at CMP. To achieve this each project should name their signals, in their TOP cell, with and ending _VLSIXXX, ie CLK_VLSI001. This makes it also possible to run LVS on the top design. Since the signal names will be unique, the schematic can be copied to one cell and an LVS can be run on the assembled chip. * The script for FIMP is working satisfactory but the metal fill script for MET4 didn't complete its work, but since CMP fills the metal layers for us this is not a problem. * Not filling all metal layers eliminate some work for the projects. The basic cells should be filled with metal if possible though, but the larger cells can be left without fill. This makes it easier to debug a design since there would be no distracting metal lying around.
Chip Assembly Tips
* Try to create a floorplan early. Make sure that all projects are aware of their floorplan and follows it. * DIVA has problems with decaps if the transistors are of different size. Try to use only one size of the transistors and base larger decaps on the smallest one. * Make the students aware of decaps and buffering of long wires relatively early in the layout phase. * Avoid using join nets for wires that are in the top cell to be assembled into the final chip, in order to avoid LVS errors that otherwise might not be detected.
* Create corners for the chip to be added to the PADS library * Check the diods in the input and output PAD that is causing DRC errors in ASSURA. * Disk space for large simulation runs are needed